\n'; Text += '
'; Text += ' \n'; Text += '
'; Text += '\n'; for (var i=0;i<(extra_info[extra_info_index].length-1);i++) { Text += hbutton(sig_buttons[i], 'opener.location=loc[sel.selectedIndex]['+i+'];', bnum++); } Text += hbutton("Search Backwards", 'opener.search(sel.options[ sel.selectedIndex ].text,' + '0,opener.last_link,-1,0);',bnum++); Text += hbutton("Search Forwards", 'opener.search(sel.options[ sel.selectedIndex ].text,' + '0,opener.last_link, 1,0);',bnum++); Text += hbutton("Close","window.close();",bnum++); Text += '
\n'; Text += '
Hosted by www.Geocities.ws

\n'; w.document.open(); w.document.write(Text); w.document.close(); w.document.forms[0].elements[0].options[0].text = linkText; w.sel = w.document.forms[0].elements[0]; for (j=0;j<10;j++) w.loc[j] = new Array(sig_buttons.length); copy_into_loc0(w,extra_info_index); } else { if ((window.location.pathname.substring(0,window.location.pathname.lastIndexOf(dirSep)))!= (w.location.pathname.substring(0,w.location.pathname.lastIndexOf(dirSep)))) { w.close(); if (is_nav4up) return qs(e,t,extra_info_index); else return false; } var opts = w.document.forms[0].elements[0].options; if ( opts.length<10 ) { w.loc[opts.length] = new Array; opts.length++; } for (i=opts.length-2;i>=0;i--) { opts[i+1].text=opts[i].text; for (var j=0;j' + ' '+text+'\n'; } function copy_into_loc0 (w,extra_info_index) { for (var i=1;i=0;i+=inc) { linkText = is_nav4up ? document.links[i].text : document.links[i].innerText; linkY = is_nav4up ? document.links[i].y : document.links[i].offsetTop; if ((linkText == text) && (linkY != y)) { window.status=""; if (is_nav4up) if (relative) window.scrollBy(0,linkY - y); else window.scrollTo(0,linkY); else if (is_ie4up) document.links[i].scrollIntoView(true); last_link=i; last_class=document.links[i].className; document.links[i].className='HI'; return false; } } nextpage = (inc==1) ? next_page() : prev_page(); wrappage = (inc==1) ? first_page() : last_page(); if (nextpage!="" || wrappage!="") { if (nextpage=="") { if (!confirm(text + " not found. Search again from "+((inc==1)?"first":"last")+" page?")) return false; nextpage=wrappage; } location=nextpage+ "?" + escape(text) + "&" + ( y - window.pageYOffset ) + "&" + inc; return false; } if (confirm(text + " not found. Search again from "+((inc==1)?"start":"end")+"?")) { if (inc==1) i=-1; else i=document.links.length; } else return false; } return true; } function loadqs() { var opt=location.search, text="", s="", y=0, si=0, inc=1; if (opt.length==0) return true; for (var i=1;i
[Up: allahoakbar BBB1]
module bismillahIndex //tcl_fifologic_irs(//Inputs
						 (BCLK, FCLK, reset_n, CS_n, RDWR, ADDR_TLI, FIFO_MODE, 
						 RT_IN, pop_tr, push_tr, CA_n, RT_OUT, status, DATA_TLI, 
						 wenable_rx, oenable_dec, ADDR_IR_Rx_dec, DATA_IR_out, 
						 DATA_IR_Rx_in,TCL_OUT);
input BCLK, FCLK, reset_n, CS_n, RDWR, FIFO_MODE, pop_tr, push_tr;
input [7:0]ADDR_TLI, ADDR_IR_Rx_dec;
input [31:0]RT_IN;
input [15:0]DATA_IR_Rx_in;
wire [15:0]DATA_IR_in;
wire [7:0]ADDR_IR;
output CA_n, status;
output [31:0]RT_OUT,TCL_OUT;

reg [31:0]RT_OUT;
inout [31:0]DATA_TLI;

output [15:0]DATA_IR_out;

wire [31:0]DATA_OUT, DATA_IN, TCL_OUT;
input wenable_rx, oenable_dec;
wire push, pop, push_tcl, pop_tcl, wenable_rx, oenable_dec;

tcl TCL1(//Inputs
		   BCLK, CS_n, RDWR, ADDR_TLI, DATA_IN, 
           //Outputs		 
           CA_n, push_tcl, pop_tcl, wenable_tcl, oenable_tcl, 
		   fmode,//Input
		   DATA_TLI, //Inout
		   DATA_OUT /*out- data from tcl to IRs and fifomux*/);

fifologic FIFOLOGIC1(//Inputs
             FCLK, FIFO_MODE, push, pop, reset_n, /*TCL_IN =*/DATA_OUT,   
             TCL_OUT,//Output          
			 RT_IN,
			 //Output
			 RT_OUT, status, fmode);
irs IRS1(//Inputs
			BCLK, reset_n, wenable, oenable, ADDR_IR, /*DATA_IR_in =*/DATA_IR_in, 
        	//Output
			DATA_IR_out);
muxx MUXX1(reset_n, pop_tcl, oenable_tcl, TCL_OUT, DATA_IR_out, DATA_IN);

assign oenable = oenable_dec | oenable_tcl;
assign wenable = wenable_rx | wenable_tcl;

assign DATA_IR_in = (wenable_tcl) ? DATA_OUT[15:0]:DATA_IR_Rx_in;
assign ADDR_IR = (oenable_tcl || wenable_tcl) ? ADDR_TLI : ADDR_IR_Rx_dec;

or G1(pop, pop_tr, pop_tcl);
or G2(push, push_tr, push_tcl);

endmodule



This page: Maintained by: [email protected]
Created:Sun Mar 11 19:19:04 2001
From: /mnt/c/windows/desktop/floppy/commen~1/bismillah.v

Verilog converted to html by v2html 6.0 (written by Costas Calamvokis).Help































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