module allahoakbarIndex(BCLK,FCLK, SCLK,reset_n, CS_n, RDWR, strobe, data_end, pop_tr, ADDR_TLI, status,DATA_TLI, monitor,
 Req_Type, D, reception, lreq, RE, ctrl_pins, ctl, ERROR,packet_error, packet_good);

input BCLK, FCLK, SCLK, reset_n, CS_n, RDWR, strobe, data_end, pop_tr;
input [7:0] ADDR_TLI;
input [2:0]monitor;
input [0:16]Req_Type;
input [7:0] D; 
output status, reception, lreq, RE,  ERROR, packet_error, packet_good;
output [2:0]ctrl_pins;
//output [31:0]CALC_CRC;
inout [31:0]DATA_TLI;
inout [1:0]ctl;

//output [31:0] RT_IN,TCL_OUT;
wire [15:0] DATA_IR_Rx_in;
wire [31:0] parallel_data, RT_IN;
wire [7:0]ADDR_IR_Rx_dec;
wire [15:0]DATA_IR_out;
wire [2:0]ctrl_pins;
 bismillah  BBB1(BCLK, FCLK, reset_n, CS_n, RDWR, ADDR_TLI, fifo_mode, 
						 RT_IN, pop_tr, push_tr, CA_n, RT_OUT, status, DATA_TLI, 
						 wenable_rx, oenable_dec, ADDR_IR_Rx_dec, DATA_IR_out, 
						 DATA_IR_Rx_in,TCL_OUT);

 mashallah MMM1( BCLK, SCLK, reset_n, strobe, packet_error, data_end,ERROR, 
				   broadcast, monitor, Req_Type, D, reception, lreq, RE, stcmp, 
				   quad_fill, parallel_data, ctrl_pins, ctl);

alhamdulillah AAA1(BCLK, reset_n, stcmp, quad_fill, ctrl_pins, parallel_data, ERROR, 
				   packet_error, packet_good, push_tr, fifo_mode, wenable_rx, oenable_dec, 
				   DATA_IR_Rx_in, ADDR_IR_Rx_dec, DATA_IR_out, data_dec_out/*kharish*/, 
					CALC_CRC/*only for check*/, RT_IN, broadcast); 

endmodule



This page: Maintained by: firewire@linklayercontroller.com
Created:Sun Mar 11 19:18:59 2001
From: /mnt/c/windows/desktop/floppy/commen~1/allahoakbar.v

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