Before discussing PCI Express, it is important to understand how far bus technology has come. Back in 1984, IBM shipped its PC AT. The CPU, memory, and I/O bus all shared a common 8MHz clock. This I/O bus became known as the ISA (Industry Standard Architecture) bus. ISA was a 16-bit interface, which meant that data could only be transferred two bytes at a time. More importantly, the ISA bus only operated at 8 MHz and typically required two or three clock signals to transfer those two bytes of data. This was not a problem for devices that were inherently slow (i.e. COM ports, printer ports, sound cards or CD-ROMs), however the ISA bus was too slow for high performance disk access and display adapters. When the ISA bus started running out of steam, other architectures were developed. Unfortunately, the Microchannel (MCA) bus, EISA and VESA Local Bus (VLB) architectures were insufficient and short lived. It was finally the PCI bus that successfully brought the much needed bandwidth to the system.
PCI is a 64 bit interface in a 32 bit package. Figuring this out requires a bit of arithmetic. The PCI bus runs at 33 MHz and can transfer 32 bits of data (four bytes) every clock tick. That sounds like a 32-bit bus. However, a clock tick at 33 MHz is 30 nanoseconds, and memory only has a speed of 70 nanoseconds. When the CPU fetches data from RAM, it has to wait at least three clock ticks for the data. By transferring data every clock tick, the PCI bus can deliver the same throughput on a 32 bit interface that other parts of the machine deliver through a 64 bit path.
While PCI was a savior when it was released, it too has run out of headroom. With faster hard drives, PCI-based sound cards, Ethernet controllers, etc., the PCI bus was beginning to act like New York City during rush hour! A new standard was needed to open up additional bandwidth.
PCI-Express (formerly 3GIO) was a development effort, led by the likes of Intel, to advance the I/O (input output) functionality of today's computers. With the ever greater demand for fast processing and with the CPU being bottlenecked by aging system busses, this development was designed to regain the balance between raw CPU speed and system speed.
for further details on bus history click the link below
extensive bus history: click here
